1. Field of the Invention
The present invention relates to processes for the formation of an integrated circuits structure and, in particular, to a process for the formation of an integrated circuit that includes metal salicide regions and metal salicide exclusion regions.
2. Description of the Related Art
In Metal-Oxide-Semiconductor (MOS) device manufacturing, self-aligned metal silicide layers (also known as "salicide" layers) are useful in reducing the sheet resistance of polysilicon interconnections, source regions and drains regions, as well as contact resistance. See, for example, Stanley Wolf, Silicon Processing for the VLSI Era, Vol. I, 388-399 (Lattice Press, 1986).
FIGS. 1-3 illustrate a conventional process for forming a metal silicide layer over a polysilicon gate, a source region and a drain region of an MOS transistor structure within an integrated circuit (IC). A conventional MOS transistor structure 10 includes a thin gate oxide layer 12 overlying P-type silicon substrate 14 between N-type drain region 16 and N-type source region 18, both of which are formed in P-type silicon substrate 14. A conventional MOS transistor structure 10 also includes a polysilicon gate 20 overlying thin gate oxide layer 12, as well as field oxide regions 22, which isolate MOS transistor structure 10 from neighboring semiconductor device structures (not shown). Gate sidewall spacers 24, typically formed of silicon dioxide and/or silicon nitride, are disposed on the lateral edges of polysilicon gate 20 and thin gate oxide layer 12.
In a conventional metal silicide formation process, a metal layer 28 is deposited over the surface of MOS transistor structure 10, as illustrated in FIG. 2. Metal layer 28 is ordinarily deposited by a multi-directional evaporative or sputtering-based physical vapor deposition (PVD) process or a multi-directional chemical vapor deposition (CVD) process and is, therefore, of essentially uniform thickness over the entire surface of MOS transistor structure 10.
Wherever metal layer 28 is in contact with silicon surfaces (i.e. source region 18, drain region 16 and the polysilicon surface of polysilicon gate 20) the metal is reacted to form a metal silicide layer. The reaction conditions, such as temperature and gaseous ambient, employed for the metal silicide layer formation are selected to foster the reaction of the metal layer with silicon surfaces while impeding the reaction of the metal layer with silicon dioxide or silicon nitride surfaces (i.e. the gate sidewall spacers and field oxide regions).
A selective etch is then used to remove unreacted metal from the surface of the gate sidewall spacers and field oxide regions, as well as any unreacted metal residue still remaining above the source region, drain region and polysilicon gate. The etch is "selective" since it does not remove the metal silicide layer that was formed on the surface of the silicon and polysilicon regions. The result, illustrated in FIG. 3, is a metal silicide layer 32 on the surface of drain region 16, a metal silicide layer 34 on the surface of source region 18 and a metal silicide layer 36 on the surface of polysilicon gate 20.
It can be desireable to form integrated circuits that include both MOS transistors structures with metal salicide layers (i.e., metal salicide regions) and MOS transistor structures without metal salicide layers (i.e., metal salicide exclusion regions). For example, it is often beneficial to form input/output (I/O) MOS transistor structures without metal salicide layers in order to provide a relatively high resistance I/O path for electrostatic discharge (ESD) protection.
Conventional processes for the formation of IC structures with metal salicide regions and metal salicide exclusion regions involve a series of steps that form a layer of silicon dioxide over MOS transistor structures where metal salicide exclusion regions are to be formed, prior to the deposition of a metal layer. This series of steps includes depositing a silicon dioxide layer on an integrated circuit structure, forming a photoresist masking layer on the silicon dioxide layer, removing the silicon dioxide layer from the MOS transistor structures where metal salicide regions are to be formed, and then stripping the photoresist masking layer. This series of steps is followed by the deposition of a metal layer and the formation of metal salicide regions.
A drawback of conventional processes for the formation of IC structures with metal salicide regions and metal salicide exclusion regions is the potential for the step of removing the silicon dioxide layer to damage the MOS transistor structures where metal salicide regions are to be formed. For example, if the silicon dioxide layer is removed from the MOS transistor structures where metal salicide regions are to be formed using an HF acid or buffered oxide etchant (BOE), then there is a potential for the HF acid and BOE to attack gate sidewall spacers formed of silicon dioxide. In addition, the conventional processes are relatively complicated and requires many steps since they involve the deposition of a silicon dioxide layer, the formation of a masking layer, the removal of the silicon dioxide layer and the stripping of the photoresist masking layer.
Still needed in the field is a process for manufacturing an integrated circuit structure with a metal salicide region(s) and a metal salicide exclusion region(s) that is simple, requires a minimum number of steps and does not subject MOS transistor structures where metal salicide regions are to be formed to damage by a silicon dioxide layer removal process step.